Education

• B.S. in Electronic Engineering, University of Rome Tor Vergata, 2016
• M.S. in Electronic Engineering for Telecommunication and Multimedia, University of Rome Tor Vergata, 2019
• Ph.D in Electronic Engineering, University of Rome Tor Vergata, 2022

Work experience

• From 04/2018 to 10/2019 Research work with CNIT, University of Rome Tor Vergata
  • Research work in EU projects SESAMO and 5G-PICTURE, POR FESR 2014/2020
• From 11/2022 to 10/2023 Assistant Researcher, Politecnico di Milano – DEIB Department
  • Research activity titled: “Design of Integrated Circuits for High-Security Primitive of In-Memory Computing”
• From 11/2023 Associate Researcher @ IRISA Lab, Inria SUSHI (SecUrity at the Software-Hardware Interface) team
  • Research focus: Hardware Security, Side-Channel Analysis, Side-Channel Attacks

Publications

hXDP: Efficient software packet processing on FPGA NICs

M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci and R. Bifulco (2020). "hXDP: Efficient software packet processing on FPGA NICs." 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20).

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses

A. Palumbo, L. Cassano, P. Reviriego, G. Bianchi and M. Ottavi (2021). "A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses." 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches

A. Palumbo, K. Arıkan, L. Cassano, P. Reviriego, S. Pontarelli, G. Bianchi, O. Ergin, M. Ottavi (2022). "Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches." IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

A. Palumbo, L. Cassano, B. Luzzi, J. A. Hernández, P. Reviriego, G. Bianchi and M. Ottavi (2022)."Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer." Journal of Systems Architecture.

hXDP: Efficient software packet processing on FPGA NICs

M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci and R. Bifulco (2022). "hXDP: Efficient software packet processing on FPGA NICs." Communications of the ACM.

Is RISC-V ready for Space? A Security Perspective

L. Cassano, S. Di Mascio, A. Palumbo, A. Menicucci, G. Furano, G. Bianchi and M. Ottavi (2022). "Is RISC-V ready for Space? A Security Perspective." 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Towards Dependable RISC-V Cores for Edge Computing Devices

P. R. Nikiema, A. Palumbo, A. Aasma, L. Cassano, A. Kritikakou, A. Kulmala, J. Lukkarila, M. Ottavi, R. Psiakis and M. Traiola (2023). "Towards Dependable RISC-V Cores for Edge Computing Devices." 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses

A. Palumbo, M. Ottavi and L. Cassano (2023). "Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses." 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

A. Palumbo, L. Cassano, P. Reviriego and M. Ottavi (2023). "Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes." 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Machine Learning-based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores

S. Ribes, F. Malatesta, G. Garzo and A. Palumbo (2024). "Machine Learning-based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores." 2024 10th International Conference on Information Systems Security and Privacy (ICISSP).

Opening the Black Box: How Boolean AI can Support Legal Analysis

G. Garzo, S. Ribes and A. Palumbo (2024). "Opening the Black Box: How Boolean AI can Support Legal Analysis." 2024 IEEE the 4th International Conference on Computer Communication and Artificial Intelligence (CCAI).

Teaching

Teaching Assistant A.Y. 2020/2021

Teaching Assistant A.Y. 2021/2022

Contract Professor A.Y. 2021/2022

Teaching Assistant A.Y. 2022/2023

Contract Professor A.Y. 2022/2023

Contract Professor A.Y. 2022/2023

Associate Professor A.Y. 2023/2024