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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
Pages
Biography
About me
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Posts
Future Blog Post
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Blog Post number 4
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Blog Post number 3
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Blog Post number 2
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Blog Post number 1
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publications
hXDP: Efficient software packet processing on FPGA NICs
Published in 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20), 2020
Best Paper Award
Recommended citation: M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci and R. Bifulco (2020). "hXDP: Efficient software packet processing on FPGA NICs." 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). https://www.usenix.org/conference/osdi20/presentation/brunella
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
Published in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021
Recommended citation: A. Palumbo, L. Cassano, P. Reviriego, G. Bianchi and M. Ottavi (2021). "A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses." 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). https://ieeexplore.ieee.org/abstract/document/9568291
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022
Recommended citation: A. Palumbo, K. Arıkan, L. Cassano, P. Reviriego, S. Pontarelli, G. Bianchi, O. Ergin, M. Ottavi (2022). "Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches." IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://ieeexplore.ieee.org/abstract/document/9777885
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
Published in Journal of Systems Architecture, 2022
Recommended citation: A. Palumbo, L. Cassano, B. Luzzi, J. A. Hernández, P. Reviriego, G. Bianchi and M. Ottavi (2022)."Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer." Journal of Systems Architecture. https://www.sciencedirect.com/science/article/abs/pii/S1383762122001023
hXDP: Efficient software packet processing on FPGA NICs
Published in Communications of the ACM, 2022
Recommended citation: M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci and R. Bifulco (2022). "hXDP: Efficient software packet processing on FPGA NICs." Communications of the ACM. https://dl.acm.org/doi/abs/10.1145/3543668
Is RISC-V ready for Space? A Security Perspective
Published in 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Recommended citation: L. Cassano, S. Di Mascio, A. Palumbo, A. Menicucci, G. Furano, G. Bianchi and M. Ottavi (2022). "Is RISC-V ready for Space? A Security Perspective." 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). https://ieeexplore.ieee.org/abstract/document/9962352
Towards Dependable RISC-V Cores for Edge Computing Devices
Published in 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023
Recommended citation: P. R. Nikiema, A. Palumbo, A. Aasma, L. Cassano, A. Kritikakou, A. Kulmala, J. Lukkarila, M. Ottavi, R. Psiakis and M. Traiola (2023). "Towards Dependable RISC-V Cores for Edge Computing Devices." 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS). https://ieeexplore.ieee.org/abstract/document/10224862
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
Published in 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023
Recommended citation: A. Palumbo, M. Ottavi and L. Cassano (2023). "Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses." 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). https://ieeexplore.ieee.org/abstract/document/10313534
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
Published in 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023
Recommended citation: A. Palumbo, L. Cassano, P. Reviriego and M. Ottavi (2023). "Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes." 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). https://ieeexplore.ieee.org/abstract/document/10313563
Machine Learning-based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores
Published in 2024 10th International Conference on Information Systems Security and Privacy (ICISSP), 2024
Recommended citation: S. Ribes, F. Malatesta, G. Garzo and A. Palumbo (2024). "Machine Learning-based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores." 2024 10th International Conference on Information Systems Security and Privacy (ICISSP). https://research.chalmers.se/publication/540930/file/540930_Fulltext.pdf
Opening the Black Box: How Boolean AI can Support Legal Analysis
Published in 2024 IEEE the 4th International Conference on Computer Communication and Artificial Intelligence (CCAI), 2024
Recommended citation: G. Garzo, S. Ribes and A. Palumbo (2024). "Opening the Black Box: How Boolean AI can Support Legal Analysis." 2024 IEEE the 4th International Conference on Computer Communication and Artificial Intelligence (CCAI). https://ieeexplore.ieee.org/abstract/document/10603017
The First Hardware Circuit Emulating Italian Road Homicides Legal Logic, DAJE!
Published in 23rd ADIS International Conference on e-Society, 2025
Recommended citation: G. Garzo and A. Palumbo (2025). "The First Hardware Circuit Emulating Italian Road Homicides Legal Logic, DAJE!." 23rd ADIS International Conference on e-Society. https://hal.science/hal-04990194
Human-in-the-Loop: Legal Knowledge Formalization in Attempto Controlled English
Published in 2025 IEEE 13th International Symposium on Digital Forensics and Security (ISDFS), 2025
Recommended citation: G. Garzo, and A. Palumbo (2025). "Human-in-the-Loop: Legal Knowledge Formalization in Attempto Controlled English." 2025 IEEE 13th International Symposium on Digital Forensics and Security (ISDFS). https://hal.science/hal-05021540
Legal & Ethical Implications of Predictive Digital Techniques in the Judicial Criminal Proceedings
Published in 2025 IEEE 13th International Symposium on Digital Forensics and Security (ISDFS), 2025
Recommended citation: G. Garzo, and A. Palumbo (2025). "Legal & Ethical Implications of Predictive Digital Techniques in the Judicial Criminal Proceedings." 2025 IEEE 13th International Symposium on Digital Forensics and Security (ISDFS). https://hal.science/hal-05021547
Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection
Published in 10th International Workshop on Malicious Software and Hardware in the Internet of Things (MAL-IoT 2025), 2025
Recommended citation: A. Palumbo and R. Salvador (2025). "Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection." 10th International Workshop on Malicious Software and Hardware in the Internet of Things (MAL-IoT). https://hal.science/hal-05044677
Detecting Program Control Flow Attacks in Microprocessors via Error Correction Code-based Hardware Security Modules
Published in 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2025), 2025
Recommended citation: A. Palumbo and R. Salvador (2025). "Detecting Program Control Flow Attacks in Microprocessors via Error Correction Code-based Hardware Security Modules." 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS). https://hal.science/hal-05055204
LAD-IXoC: Loop-based Attack Detection with Integrated XOR Filter and CMS
Published in 2025 IEEE International Conference on Dependable and Fault Tolerant Systems (DFTS), 2025
Recommended citation: R. B. Martinez Aguilar and A. Palumbo and P. Reviriego and R. Salvador and D. Larrabeiti (2025). "LAD-IXoC: Loop-based Attack Detection with Integrated XOR Filter and CMS." 2025 IEEE International Conference on Dependable and Fault Tolerant Systems (DFTS). https://hal.science/hal-05195618
talks
Talk 1 on Relevant Topic in Your Field
Published:
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Conference Proceeding talk 3 on Relevant Topic in Your Field
Published:
This is a description of your conference proceedings talk, note the different field in type. You can put anything in this field.
teaching
Teaching Assistant A.Y. 2020/2021
Engineering Bachelor Degrees, University of Rome Tor Vergata, Information Engineering and Industrial Engineering Departments, 2020
Teaching Assistant for Mathematical Analysis I, 8037484, 12 CFU, MAT/05
Teaching Assistant A.Y. 2021/2022
Engineering Bachelor Degrees, University of Rome Tor Vergata, Information Engineering and Industrial Engineering Departments, 2021
Teaching Assistant for Mathematical Analysis I, 8037484, 12 CFU, MAT/05
Contract Professor A.Y. 2021/2022
Bachelor Degree in Computer Science, University of Milan Bicocca, Computer Science Department, 2021
Contract Professor for Programming 1, 2122-1-E3101Q105, 2 CFU, INF/01
Teaching Assistant A.Y. 2022/2023
Bachelor Degree in Biomedical Engineering, Politecnico di Milano, Department of Electronics, Information and Bioengineering (DEIB), 2022
Teaching Assistant for Computer Science and Element of Medical Informatics, 085851, 7 CFU, ING-INF/0
Contract Professor A.Y. 2022/2023
Bachelor Degree in Digital Electornics, Politecnico di Milano, Department of Electronics, Information and Bioengineering (DEIB), 2022
Contract Professor for IT Systems and Services, INGDIG2-3, 10 CFU
Contract Professor A.Y. 2022/2023
Bachelor Degree in Digital Electornics, Politecnico di Milano, Department of Electronics, Information and Bioengineering (DEIB), 2022
Contract Professor for Logical Networks, INGDIG2-3, 5 CFU
Associate Professor A.Y. 2023/2024
Master Degree in Cybersecurity, CentraleSupeléc, University of Paris Saclay, School of Engineering, 2023
Associate Professor for “Advanced Computer Networks” course, 2EL6110, Workload (HEE): 60